1. Field of the Invention
The present invention relates to integrated circuits generally and more specifically to a FIFO buffer having programmable serial-parallel-serial conversion.
2. Description of the Prior Art
A FIFO (first-in-first-out) buffer is a shift register having an additional control section that permits input data to "fall through" to the first vacant stage. In other words, if there is data stored in the FIFO buffer, it is available at the output even though all of the stages are not filled. Thus, in effect, a FIFO buffer operates as a "variable-length" shift register, the length of which is always the same as the data stored therein. (Of late, many FIFO buffers are implemented with random access memories and counters.)
As such, FIFO buffers are particularly suited for use in applications in which there is a need to compensate for differences in the rate of flow of data. (For example, FIFO buffers are particularly suited for use in storing data which is to be encoded and to be written onto a disk and/or which has been read off of a disk and has been decoded. Also, FIFO buffers are particularly suited for use in storing data representing the individual dots comprising a frame of a video display before the dots are clocked out to drive the display. Further, FIFO buffers are particularly suited for use in storing data which is to be transmitted and/or which has been received in a data acquisition system.)
Many of these applications, however, also require that the format of the data be converted from serial-to-parallel and/or from parallel-to-serial format. Of course, circuitry is available which will perform the necessary serial-to-parallel and/or parallel-to-serial format conversion. Unfortunately, the use of additional circuitry adds to the system cost and complexity. Further, most serial-to-parallel and/or parallel-to-serial format conversion circuitry is designed for a specific (common) word length (number of bits) which may not be optimal for the particular application.